A data transfer apparatus is proposed which controls the throughput of a data processing device between a pre-stage buffer memory and a post-stage buffer memory according to the used amounts of the pre-stage buffer memory and the post-stage buffer memory.
A packet transfer apparatus is proposed which realizes power saving by predicting a band to be used and increasing/decreasing the transfer performance on the basis of information transmitted and received between terminals.
Japanese Laid-open Patent Publication No. 2008-42654 and Japanese Laid-open Patent Publication No. 2009-147615 are examples of related art.